Capacitor structures for semiconductor integrated circuits include metal-oxide-semiconductor (MOS) capacitors, PN junction capacitors, and polysilicon-insulator-polysilicon (PIP) capacitors. Each of these capacitor structures includes at least one monocrystalline silicon layer or polycrystalline silicon layer which is used as a capacitor electrode. The use of silicon for the capacitor electrode, however, may result in a higher electrode resistance than is desired.
It is thus desirable to reduce the resistance of capacitor electrodes to decrease frequency dependence of the capacitor. Accordingly, metal-insulator-metal (MIM) thin film capacitors have been developed to provide low electrode resistances. Accordingly, metal-insulator-metal capacitors can be used in integrated circuits requiring high speed performance. In addition, metal-insulator-metal thin film capacitors have been applied to advanced analog semiconductor devices because these capacitors have capacitance fluctuation rates dependent on voltage and temperature which are sufficiently low to provide desirable electrical characteristics.
In addition, there have been efforts to reduce thicknesses of dielectric layers for integrated circuit capacitors to thereby increase the performance of capacitors including these thinner dielectric layers. In particular, the capacitance of a capacitor can be increased by reducing the thickness of the dielectric layer between the two capacitor electrodes. There have also been efforts to increase capacitances by using dielectric layers having relatively high dielectric constants, and by increasing the surface areas of the capacitor electrodes. Furthermore, multi-wiring processes have been applied to semiconductor manufacturing methods to facilitate the development of high-density integration and micro-technology. Accordingly, metal--insulator-metal thin film capacitors can be manufactured together with multi-wiring structures.
FIGS. 1 through 4 are cross-sectional views illustrating steps of a method for forming a metal-insulator-metal thin film capacitor in accordance with a multi-wiring structure. As shown in FIG. 1, an insulating layer 10 is formed on a microelectronic substrate 9. This insulating layer insulates and protects structures formed in and on the microelectronic substrate. In addition, contact holes in the insulating layer 10 can provide contact with portions of the structures previously formed in the microelectronic substrate. An aluminum layer is then formed on the insulating layer 10, and a titanium nitride (TiN) layer is formed on the aluminum layer opposite the insulating layer 10. In particular, the titanium nitride layer can reduce the formation of aluminum hillocks on the aluminum layer. The aluminum and titanium nitride layers are then patterned using photolithography and etch steps to form the first wiring layer 12b, the lower capacitor electrode 12a, and the conductive layer 14 thereon. In particular, the first-wiring layer 12b can be used to provide connections between the lower capacitor electrode 12a and other elements of the integrated circuit device.
As shown in FIG. 2, a second insulating layer 16 is deposited on the lower capacitor electrode 12a, the first-wiring layer 12b, the conductive layer 14, and the first insulating layer 10. The insulating layer 16 and the conductive layer 14 are then patterned to provide a contact hole 18 exposing a portion of the lower capacitor electrode 12a opposite the first insulating layer 10. In particular, the contact hole can be formed using photolithography and etch steps.
As shown in FIG. 3, a silicon oxide layer is deposited on the surface of the insulating layer 16 and the exposed portion of the lower capacitor electrode 12a using a chemical vapor deposition (CVD) step. This silicon oxide layer provides a dielectric layer 20 for the MIM capacitor. The insulating layer 16 and the dielectric layer 20 are then patterned to form the second contact hole 24 exposing a portion of the first wiring layer 12b opposite the first insulating layer 10. The second contact hole 24 can be formed using photolithography and etch steps.
A sputter etching step is then used to remove undesired materials (contaminants or pollutants) such as natural oxides from the exposed portion of the first wiring layer 12b, as shown in FIG. 4. An aluminum layer is then deposited and patterned to provide the upper capacitor electrode 26a and the second electrode wiring layer 26b. In particular, a continuous aluminum layer can be deposited and then patterned using photolithography and etch steps. The dielectric layer 20, however, is exposed during the sputter etching step. Accordingly, partial etching of the dielectric layer 20 may result in damage thereto as indicated by reference number 28 in FIG. 4. The homogeneity of the dielectric layer 20 may thus be reduced, and in severe cases, current leakage paths may be formed between the two capacitor electrodes.
To reduce the effects of damage to the dielectric layer 20, structures have been formed including dielectric layers with thickness of more than 1,000 Angstroms. In particular, the Japanese Patent Laid-Open No. 5-299581 includes a dielectric oxide layer with a 1,300 Angstrom thickness. The capacitance per unit area of a capacitor including such a thick dielectric layer may be reduced. Accordingly, conventional thin film capacitors may be unable to provide the speed and capacitance desired for many integrated circuit devices. Thinner dielectric layers may be unable to provide the desired performance when formed using a multi-wiring process.